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general description the max1566/max1567 provide a complete power- supply solution for digital cameras. they improve perfor- mance, component count, and size compared to con- ventional multichannel controllers in 2-cell aa, 1-cell lithium-ion (li+), and dual-battery designs. on-chip mosfets provide up to 95% efficiency for critical power supplies, while additional channels operate with external fets for optimum design flexibility. this optimizes overall efficiency and cost, while also reducing board space. the max1566/max1567 include six high-efficiency dc- to-dc conversion channels: step-up dc-to-dc converter with on-chip power fets main dc-to-dc converter with on-chip fets, config- urable to step either up or down step-down core dc-to-dc converter with on-chip fets dc-to-dc controller for white leds or other output extra dc-to-dc controller (typically for lcd); two extra controllers on the max1566 transformerless inverting dc-to-dc controller (typi- cally for negative ccd bias) on the max1567 all dc-to-dc channels operate at one fixed frequency settable from 100khz to 1mhz to optimize size, cost, and efficiency. other features include soft-start, power-ok outputs, and overload protection. the max1566/ max1567 are available in space-saving 40-pin thin qfn packages. an evaluation kit is available to expedite designs. applications digital cameras pdas features ? 95% efficient step-up dc-to-dc converter ? 0.7v minimum input voltage ? main dc-to-dc configurable as either step-up or step-down ? combine step-up and step-down for 90% efficient boost-buck ? 95% efficient step-down for dsp core ? regulate led current for four, six, or more leds ? open led overvoltage protection ? transformerless inverting controller (max1567) ? three extra pwm controllers (two on the max1567) ? up to 1mhz operating frequency ? 1a shutdown mode ? soft-start and overload protection ? compact 40-pin 6mm x 6mm thin qfn package max1566/max1567 six-channel, high-efficiency, digital camera power supplies ________________________________________________________________ maxim integrated products 1 40 36 37 38 39 18 21 23 22 24 25 19 20 16 17 6 5 4 3 2 1 7 8 9 10 11 12 13 14 15 26 27 28 29 30 31 32 33 34 35 ccsd ccm on3 max1566/max1567 top view fb3l cc3 pv dl1 dl3 dl2 gnd indl2 fb2 susd onm fbm ccsu ref onsu fbsu scf cc2 on2 pvm lxm pgm pvsu lxsu pgsu osc fbsd onsd pvsd lxsd pgsd on1 fb1 cc1 fb3h aux1ok sdok 6mm x 6mm thin qfn pin configuration ordering information 19-2882; rev 1; 4/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin-package aux2 function max1566 etl -40 c to +85 c 40 thin qfn 6mm x 6mm step-up controller max1567 etl -40 c to +85 c 40 thin qfn 6mm x 6mm inverting controller li+ or 2aa battery input system 5v 3.3v logic 1.8v core leds ccd/lcd + 15v ccd - 7.5v step-up main dc-to-dc step-dn aux3 aux1 aux2 onsu onm onsd on3(led) on1 on2 max1567 t ypical operating circuit
max1566/max1567 six-channel, high-efficiency, digital camera power supplies 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. pv, pvsu, sdok , aux1ok , scf, on_, fb_, susd to gnd ....................................................... -0.3v to +6v pg_ to gnd...........................................................-0.3v to +0.3v dl1, dl3, indl2, pvm, pvsd to gnd ?0.3v to (pvsu + 0.3v) dl2 to gnd ............................................-0.3v to (indl2 + 0.3v) lxsu current (note 1) ..........................................................3.6a lxm current (note 1) ............................................................3.6a lxsd current (note 1) ........................................................2.25a ref, osc, cc_ to gnd...........................-0.3v to (pvsu + 0.3v) continuous power dissipation (t a = +70?) 40-pin thin qfn (derate 26.3mw/? above +70?) .2105mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? electrical characteristics (v pvsu = v pv = v pvm = v pvsd = v indl2 = 3.6v, t a = 0c to +85c , unless otherwise noted.) parameter conditions min typ max units general input voltage range (note 2) 0.7 5.5 v step-up minimum startup voltage (note 2) i load < 1ma, t a = +25 c; startup voltage tempco is -2300ppm/ c (typ) (note 3) 0.9 1.1 v shutdown supply current into pv pv = 3.6v 0.1 10 ? supply current into pv with step- up enabled onsu = 3.6v, fbsu = 1.5v (does not include switching losses) 300 450 ? supply current into pv with step- up and step-down enabled onsu = onsd = 3.6v, fbsu = 1.5v, fbsd = 1.5v (does not include switching losses) 450 700 ? supply current into pv with step- up and main enabled onsu = onm = 3.6v, fbsu = 1.5v, fbsd = 1.5v (does not include switching losses) 450 700 ? total supply current from pv and pvsu with step-up and one aux enabled onsu = on1 = 3.6v, fbsu = 1.5v, fb2 = 1.5v (does not include switching losses) 400 650 ? reference reference output voltage i ref = 20? 1.23 1.25 1.27 v reference load regulation 10? < i ref < 200? 4.5 10 mv reference line regulation 2.7 < pvsu < 5.5v 1.3 5 mv oscillator osc discharge trip level rising edge 1.225 1.25 1.275 v osc discharge resistance osc = 1.5v, i osc = 3ma 52 80 ? osc discharge pulse width 200 ns osc frequency r osc = 47k ? , c osc = 100pf 500 khz note 1: lxsu has internal clamp diodes to pvsu and pgsu, lxm has internal clamp diodes to pvm and pgm, and lxsd has inter- nal clamp diodes to pvsd and pgsd. applications that forward bias these diodes should take care not to exceed the devices?power dissipation limits.
max1566/max1567 six-channel, high-efficiency, digital camera power supplies _______________________________________________________________________________________ 3 electrical characteristics (continued) (v pvsu = v pv = v pvm = v pvsd = v indl2 = 3.6v, t a = 0c to +85c , unless otherwise noted.) parameter conditions min typ max units step-up dc-to-dc step-up startup-to-normal operating threshold rising edge or falling edge (note 4) 2.30 2.5 2.65 v step-up startup-to-normal operating threshold hysteresis 80 mv step-up voltage adjust range 3.0 5.5 v start delay of onsd, onm, on1, on2, and on3 after su in regulation 1024 osc cycles fbsu regulation voltage 1.231 1.25 1.269 v fbs u to c c s u tr ans cond uctance fbsu = ccsu 80 135 185 ? fbsu input leakage current fbsu = 1.25v -100 0.01 +100 na idle mode tm trip level 150 ma current-sense amplifier transresistance 0.275 v/a step-up maximum duty cycle fbsu = 1v 80 85 90 % pvsu leakage current v lx = 0v, pvsu = 3.6v 0.1 5 ? lxsu leakage current v lx = v out = 3.6v 0.1 5 ? n channel 95 150 switch on-resistance p channel 150 250 m ? n-channel current limit 1.8 2.1 2.4 a p-channel turn-off current 20 ma startup current limit pvsu = 1.8v (note 5) 450 ma startup t off pvsu = 1.8v 700 ns startup frequency pvsu = 1.8v 200 khz main dc-to-dc converter main step-up voltage adjust range susd = pvsu 3 5.5 v main step-down voltage adjust range susd = gnd, pvm must be greater than output (note 6) 2.45 5.00 v pvm undervoltage lockout in step-down mode susd = gnd (note 6) 2.45 2.5 2.55 v regulation voltage 1.231 1.25 1.269 v fbm to ccm transconductance fbm = ccm 80 135 185 ? fbm input leakage current fbm = 1.25v -100 0.01 +100 na step-up mode (susd = pvsu) 150 idle mode trip level step-down mode (susd = gnd) 100 ma step-up mode (susd = pvsu) 0.25 current-sense amplifier transresistance step-down mode (susd = gnd) 0.5 v/a idle mode is a trademark of maxim integrated products, inc.
max1566/max1567 six-channel, high-efficiency, digital camera power supplies 4 _______________________________________________________________________________________ electrical characteristics (continued) (v pvsu = v pv = v pvm = v pvsd = v indl2 = 3.6v, t a = 0c to +85c , unless otherwise noted.) parameter conditions min typ max units step-up mode (susd = pvsu) 80 85 90 maximum duty cycle (note 6) step-down mode (susd = gnd) 95 % lxm leakage current v lxm = 0 to 3.6v, pvsu = 3.6v 0.1 5 ? n channel 95 150 switch on-resistance p channel 150 250 m ? step-up mode (susd = pvsu) 1.8 2.1 2.4 main switch current limit step-down mode (susd = gnd) 0.70 0.8 0.95 a step-up mode (susd = pvsu) 20 synchronous rectifier turn-off current step-down mode (susd = gnd) 20 ma soft-start interval 4096 osc cycles step-down dc-to-dc converter step-down output-voltage adjust range pvsd must be greater than output (note 7) 1.25 5.00 v fbsd regulation voltage 1.231 1.25 1.269 v fbsd to ccsd transconductance fbsd = ccsd 80 135 185 ? fbsd input leakage current fbsd = 1.25v -100 0.1 +100 na idle mode trip level 100 ma current-sense amplifier transresistance 0.5 v/a lxsd leakage current v lxsd = 0 to 3.6v, pvsu = 3.6v 0.1 5 ? n channel 95 150 switch on-resistance p channel 150 250 m ? p-channel current limit 0.65 0.77 0.90 a n-channel turn-off current 20 ma soft-start interval 2048 osc cycles sdok output low voltage 0.1ma into sdok 0.01 0.1 v sdok leakage current onsu = gnd 0.01 1 ? aux1, 2, 3 dc-to-dc controllers indl2 undervoltage lockout 2.45 2.5 2.55 v maximum duty cycle fb_ = 1v 80 85 90 % fb1, fb2 (max1566), fb3h regulation voltage 1.231 1.25 1.269 v fb2 (max1567) inverter regulation voltage -0.01 0 +0.01 v
max1566/max1567 six-channel, high-efficiency, digital camera power supplies _______________________________________________________________________________________ 5 electrical characteristics (continued) (v pvsu = v pv = v pvm = v pvsd = v indl2 = 3.6v, t a = 0c to +85c , unless otherwise noted.) parameter conditions min typ max units fb3l regulation voltage 0.19 0.2 0.21 v aux1, aux2 fb to cc transconductance 80 135 185 ? aux3 fbl or fbh to cc transconductance 50 100 150 ? fb_ input leakage current -100 0.1 +100 na dl_ driver resistance output high or low 2.5 7 ? dl_ drive current sourcing or sinking 0.5 a soft-start interval 4096 osc cycles aux1ok output low voltage 0.1ma into aux1ok 0.01 0.1 v aux1ok leakage current onsu = gnd 0.01 1 ? overload protection overload protection fault delay 100,000 osc cycles scf leakage current onsu = pvsu, fbsu = 1.5v 0.1 1 ? scf output low voltage 0.1ma into scf 0.01 0.1 v thermal-limit protection thermal shutdown 160 c thermal hysteresis 20 c logic inputs (on_, susd) 1.1v < pvsu < 1.8v 0.2 1.8v pvsu < 2.5v 0.4 onsu input low level 2.5v pvsu < 5.5v 0.5 v 1.1v < pvsu < 1.8v (pvsu - 0.2) onsu input high level 1.8v < pvsu < 5.5v 1.6 v onm, onsd, on1, on2, on3, susd input low level 2.7v < pvsu < 5.5v (note 8) 0.5 v onm, onsd, on1, on2, on3, susd input high level 2.7v < pvsu < 5.5v (note 8) 1.6 v susd input leakage 0.1 1 ? on_ impedance to gnd 330 k ?
max1566/max1567 six-channel, high-efficiency, digital camera power supplies 6 _______________________________________________________________________________________ electrical characteristics (v pvsu = v pv = v pvm = v pvsd = v indl2 = 3.6v, t a = -40c to +85c , unless otherwise noted.) parameter conditions min max units general input voltage range (note 2) 0.7 5.5 v step-up minimum startup voltage (note 2) i load < 1ma, t a = +25 c; startup voltage tempco is -2300ppm/ c (typ) (note 3) 1.1 v shutdown supply current into pv pv = 3.6v 10 ? supply current into pv with step- up enabled onsu = 3.6v, fbsu = 1.5v (does not include switching losses) 400 ? supply current into pv with step- up and step-down enabled onsu = onsd = 3.6v, fbsu = 1.5v, fbsd = 1.5v (does not include switching losses) 600 ? supply current into pv with step- up and main enabled onsu = onm = 3.6v, fbsu = 1.5v, fbsd = 1.5v (does not include switching losses) 600 ? total supply current from pv and pvsu with step-up and one aux enabled onsu = on1 = 3.6v, fbsu = 1.5v, fb2 = 1.5v (does not include switching losses) 550 ? reference reference output voltage i ref = 20? 1.23 1.27 v reference load regulation 10? < i ref < 200? 10 mv reference line regulation 2.7v < pvsu < 5.5v 5 mv oscillator osc discharge trip level rising edge 1.225 1.275 v osc discharge resistance osc = 1.5v, i osc = 3ma 80 ? step-up dc-to-dc converter step-up startup-to-normal operating threshold rising edge or falling edge (note 4) 2.30 2.65 v step-up voltage adjust range 3.0 5.5 v fbsu regulation voltage 1.231 1.269 v fbsu to ccsu transconductance fbsu = ccsu 80 185 ? fbsu input leakage current fbsu = 1.25v -100 +100 na step-up maximum duty cycle fbsu = 1v 80 90 % pvsu leakage current v lx = 0v, pvsu = 3.6v 5 ? lxsu leakage current v lx = v out = 3.6v 5 ? n channel 150 switch on-resistance p channel 250 m ? n-channel current limit 1.8 2.4 a main dc-to-dc converter main step-up voltage adjust range susd = pvsu 3.0 5.5 v
max1566/max1567 six-channel, high-efficiency, digital camera power supplies _______________________________________________________________________________________ 7 electrical characteristics (continued) (v pvsu = v pv = v pvm = v pvsd = v indl2 = 3.6v, t a = -40c to +85c , unless otherwise noted.) parameter conditions min max units main step-down voltage adjust range susd = gnd, pvm must be greater than output (note 6) 2.45 5.00 v pvm undervoltage lockout in step-down mode susd = gnd (note 6) 2.45 2.55 v regulation voltage 1.225 1.275 v fbm to ccm transconductance fbm = ccm 80 185 ? fbm input leakage current fbm = 1.25v -100 +100 na maximum duty cycle step-up mode (susd = pvsu), step-down mode (susd = gnd) (note 6) 80 90 % lxm leakage current v lxm = 0 to 3.6v, pvsu = 3.6v 5 ? n channel 150 switch on-resistance p channel 250 m ? step-up mode (susd = pvsu) 1.8 2.4 main switch current limit step-down mode (susd = gnd) 0.70 0.95 a step-down dc-to-dc converter step-down output voltage adjust range pvsd must be greater than output (note 7) 1.25 5.00 v fbsd regulation voltage 1.225 1.275 v fbsd to ccsd transconductance fbsd = ccsd 80 185 ? fbsd input leakage current fbsd = 1.25v -100 +100 na lxsd leakage current v lxsd = 0 to 3.6v, pvsu = 3.6v 5 ? n channel 150 switch on-resistance p channel 250 m ? p-channel current limit 0.65 0.90 a sdok output low voltage 0.1ma into sdok 0.1 v sdok leakage current onsu = gnd 1 ? aux1, 2, 3 dc-to-dc controllers indl2 undervoltage lockout 2.45 2.55 v maximum duty cycle fb_ = 1v 80 90 % fb1, fb2 (max1566), fb3h regulation voltage 1.225 1.275 v fb2 (max1567) inverter regulation voltage -0.01 +0.01 v fb3l regulation voltage 0.19 0.21 v aux1, aux2 fb to cc transconductance 80 185 ?
max1566/max1567 six-channel, high-efficiency, digital camera power supplies 8 _______________________________________________________________________________________ electrical characteristics (continued) (v pvsu = v pv = v pvm = v pvsd = v indl2 = 3.6v, t a = -40c to +85c , unless otherwise noted.) parameter conditions min max units aux3 fbl or fbh to cc transconductance 35 150 ? fb_ input leakage current -100 +100 na dl_ driver resistance output high or low 7 ? aux1ok output low 0.1ma into aux1ok 0.1 v aux1ok leakage current onsu = gnd 1 ? overload protection scf leakage current onsu = pvsu, fbsu = 1.5v 1 ? scf output low voltage 0.1ma into scf 0.1 v logic inputs (on_, susd) 1.1v < pvsu < 1.8v 0.2 1.8v pvsu < 2.5v 0.4 onsu input low level 2.5v pvsu < 5.5v 0.5 v 1.1v < pvsu < 1.8v (pvsu - 0.2) onsu input high level 1.8v < pvsu < 5.5v 1.6 v onm, onsd, on1, on2, on3, susd input low level 2.7v < pvsu < 5.5v (note 8) 0.5 v onm, onsd, on1, on2, on3, susd input high level 2.7v < pvsu < 5.5v (note 8) 1.6 v susd input leakage 1 ? note 2: the max1566/max1567 are powered from the step-up output (pvsu). an internal low-voltage startup oscillator drives the step-up starting at approximately 0.9v until pvsu reaches approximately 2.5v. when pvsu reaches 2.5v, the main control circuitry takes over. once the step-up is up and running, it can maintain operation with very low input voltages; however, output current is limited. note 3: since the device is powered from pvsu, a schottky rectifier, connected from the battery to pvsu, is required for low-voltage startup. note 4: the step-up regulator is in startup mode until this voltage is reached. do not apply full load current during startup. a power- ok output can be used with an external pfet to gate the load until the step-up is in regulation. see the aux1ok , sdok , and scf connections section. note 5: the step-up current limit in startup refers to the lxsu switch current limit, not the output current limit. note 6: if the main converter is configured as a step-up (susd = pvsu), the p-channel synchronous rectifier is disabled until the 2.5v normal operation threshold has been exceeded. if the main converter is configured as a step-down (susd = gnd), all step-down operation is locked out until the normal operation threshold has been exceeded. when the main is configured as a step-down, operation in dropout (100% duty cycle) can only be maintained for 100,000 osc cycles before the output is considered faulted, triggering global shutdown. note 7: operation in dropout (100% duty cycle) can only be maintained for 100,000 osc cycles before the output is considered faulted, triggering global shutdown. note 8: onm, onsd, on1, on2, and on3 are disabled until 1024 osc cycles after pvsu reaches 2.7v.
max1566/max1567 six-channel, high-efficiency, digital camera power supplies _______________________________________________________________________________________ 9 90 0 1 1000 100 10 step-up efficiency vs. load current 30 10 70 50 100 40 20 80 60 max1566/67 toc01 load current (ma) efficiency (%) v in = 4.5v v in = 3.8v v in = 3.2v v in = 2.5v v in = 2.0v v in = 1.5v v su = 5v 90 0 1 1000 100 10 main (step-up) efficiency vs. load current 30 10 70 50 100 40 20 80 60 max1566/67 toc02 output current (ma) efficiency (%) v in = 3.2v v in = 2.5v v in = 2.0v v in = 1.5v v m = 3.3v 90 0 1 1000 100 10 boost-buck efficiency (su + main as step-down) vs. load current 30 10 70 50 100 40 20 80 60 max1566/67 toc03 output current (ma) efficiency (%) v in = 4.5v v in = 3.8v v in = 3.2v v in = 2.5v v m = 3.3v v su = 5v 90 0 1 1000 100 10 step-down efficiency vs. load current 30 10 70 50 100 40 20 80 60 max1566/67 toc04 load current (ma) efficiency (%) v in = 2.5v v in = 3.0v v in = 3.8v v in = 4.5v sd = 1.8v sd input connected to batt 90 10 1 1000 100 10 boost-buck efficiency (su + sd) vs. load current 40 20 70 100 50 30 80 60 max1566/67 toc05 load current (ma) efficiency (%) v in = 3.2v v in = 2.5v v in = 2.0v v in = 1.5v v su = 3.3v sd = 1.8v 100 95 90 85 80 75 70 1.5 2.5 3.5 4.5 efficiency vs. input voltage max1566/67 toc06 input voltage (v) efficiency (%) su + sd, i out3 = 350ma v m = 3.3v i outvm = 200ma su = 5v, i outsu = 500ma aux2 = 8v, i out2 = 100ma 80 0 1 1000 100 10 aux efficiency vs. load current 30 10 60 90 40 20 70 50 max1566/67 toc07 load current (ma) efficiency (%) v in = 4.5v v in = 3.8v v in = 3.0v v in = 2.0v v in = 1.5v v out_aux = 5v 110 100 aux efficiency vs. load current max1566/67 toc08 load current (ma) 90 30 50 40 80 100 60 70 efficiency (%) v in = 4.5v v in = 3.8v v in = 3.0v v in = 2.0v v in = 1.5v v out_aux = 15v 90 0 10 1 1000 100 10 max1567 aux2 efficiency vs. load current 40 20 70 100 50 30 80 60 max1566/67 toc09 load current (ma) efficiency (%) v in = 2.5v v in = 3.0v v in = 3.8v v in = 4.5v v aux2 = -7.5v t ypical operating characteristics (t a = +25?, unless otherwise noted.)
max1566/max1567 six-channel, high-efficiency, digital camera power supplies 10 ______________________________________________________________________________________ t ypical operating characteristics (continued) (t a = +25?, unless otherwise noted.) 0.5 1.0 1.5 2.0 2.5 3.0 02 1345 no-load input current vs. input voltage (switching) max1566/67 toc10 input voltage (v) input current (ma) v su = 5.0v only v su = 5.0v + v sd = 1.8v v su = 5.0v + v m = 3.3v 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 600 200 400 800 1000 minimum startup voltage vs. load current (outsu) max1566/67 toc11 load current (ma) minimum startup voltage (v) with no schottky rectifer from batt to pvsu 1.251 1.248 1.246 1.243 -50 25 -25 0 50 75 100 reference voltage vs. temperature max1566/67 toc12 temperature ( c) reference voltage (v) 1.254 1.250 1.249 1.248 1.247 1.246 1.245 1.244 0 100 200 300 50 150 250 reference voltage vs. reference load current max1566/67 toc13 reference load current ( a) reference voltage (v) 0 1 1000 100 10 oscillator frequency vs. r osc 400 800 600 200 1000 max1566/7 toc14 r osc (k ? ) oscillator frequency (khz) c osc = 470pf c osc = 330pf c osc = 220pf c osc = 100pf c osc = 47pf 315 314 313 312 311 310 309 308 307 306 305 304 303 302 301 300 -50 25 -25 0 50 75 100 switching frequency vs. temperature max1566/67 toc15 temperature ( c) switching frequency (khz) 88 87 86 85 84 83 82 81 80 0 600 200 400 800 1000 1200 aux_ maximum duty cycle vs. frequency max1566/67 toc16 frequency (khz) maximum duty cycle (%) when this duty cycle is exceeded for 100,000 clock cycles, the max1566/max1567 shut down c osc = 100pf step-up startup waveforms max1566/67 toc17 100 s/div i in 1a/div onsu 2v/div v su = 3.3v 5v/div i out_su 100ma/div v in = 2v, v su = 3.3v 0v 0v 0a 0a step-up startup waveforms max1566/67 toc18 100 s/div i in 1a/div onsu 2v/div v su = 5v 5v/div i out_su 100ma/div v in = 3.0v, v su = 5v 0v 0v 0a 0a
max1566/max1567 six-channel, high-efficiency, digital camera power supplies ______________________________________________________________________________________ 11 main (step-up mode) and step-down startup waveforms max1566/67 toc19 2ms/div v m (main as boost) 2v/div onsu = onsd = onm 2v/div v su 5v/div v sd 1v/div v in = 3.0v 0v 0v 0v 0v main (step-down mode) and step-down startup waveforms max1566/67 toc20 2ms/div v m 2v/div onsu = onm = onsd 2v/div v su 2v/div v sd 2v/div 0v 0v 0v 0v main as a step-down step-up load transient response max1566/67 toc21 1ms/div i su 200ma/div v su ac-coupled 100mv/div v in = 3.0v, v su = 5v 0v 0a main (step-up mode) load transient response max1566/67 toc22 1ms/div i m 100ma/div v m ac-coupled 100mv/div (main as step-up) v in = 3.0v, v m = 3.3v 0v 0a main (step-down mode) load transient response max1566/67 toc23 1ms/div i m 200ma/div v m ac-coupled 200mv/div (main as step-down from su) v in = 3.0v, v m = 3.3v 0v 0a step-down transient response max1566/67 toc24 1ms/div isd 100ma/div v sd ac-coupled 20mv/div v in = 3.0v, v sd = 1.8v 0v 0a t ypical operating characteristics (continued) (t a = +25?, unless otherwise noted.)
max1566/max1567 six-channel, high-efficiency, digital camera power supplies 12 ______________________________________________________________________________________ pin description pin name function 1 fb3h aux3 controller voltage feedback input. connect a resistive voltage-divider from the step-up converter output to fbh to set the output voltage. the feedback threshold is 1.25v. this pin is high impedance in shutdown. fb3h can provide conventional voltage feedback (with fb3l grounded) or open-led protection in white led drive circuits. 2 cc1 aux1 controller compensation node. connect a series resistor-capacitor from this pin to gnd to compensate the converter control loop. this pin is actively driven to gnd in shutdown, overload, and thermal limit. see the aux compensation section. 3 fb1 aux1 controller feedback input. the feedback threshold is 1.25v. this pin is high impedance in shutdown. 4 on1 aux1 controller on/off input. logic high = on; however, turn-on is locked out until 1024 osc cycles after the step-up has reached regulation. this pin has an internal 330k ? pulldown resistance to gnd. 5 pgsd power ground. connect all pg_ pins to gnd with short wide traces as close to the ic as possible. 6 lxsd step-down converter switching node. connect to the inductor of the step-down converter. lxsd is high impedance in shutdown. 7 pvsd step-down converter input. bypass to gnd with a 1? ceramic capacitor. the step-down efficiency is measured from this input. 8 onsd step-down converter on/off control input. logic high = on; however, turn-on is locked out until 1024 osc cycles after the step-up has reached regulation. this pin has an internal 330k ? pulldown resistance to gnd. 9 fbsd step-down converter feedback input. the feedback threshold is 1.25v. this pin is high impedance in shutdown. 10 ccsd step-down converter compensation node. connect a series resistor-capacitor from this pin to gnd for compensating the converter control loop. this pin is actively driven to gnd in shutdown, overload, and thermal limit. see the step-down compensation section. 11 susd configures the main converter as a step-up or a step-down. this function must be hardwired. on- the-fly changes are not allowed. with susd connected to pv, the main is configured as a step-up and pvm is the converter output. with susd connected to gnd, the main is configured as a step- down and pvm is the power input. 12 ccm main converter compensation node. connect a series resistor-capacitor from this pin to gnd for compensating the converter control loop. this pin is actively driven to gnd in shutdown, overload, and thermal limit. see the step-up compensation section when the main is used in step-up mode and the step-down compensation section when the main is used in step-down mode. 13 fbm main converter feedback input. the feedback threshold is 1.25v. this pin is high impedance in shutdown. the main output voltage must not be set higher than the step-up output. 14 onm on/off control for the main dc-to-dc converter. logic high = on; however, turn-on is locked out until 1024 osc cycles after the step-up has reached regulation. this pin has an internal 330k ? pulldown resistance to gnd. susd pin configures the main converter as a step-up or step-down. 15 ref reference output. bypass ref to gnd with a 0.1? or greater capacitor. the maximum-allowed ref load is 200?. ref is actively pulled to gnd when the step-up is shut down (all converters turn off).
max1566/max1567 six-channel, high-efficiency, digital camera power supplies ______________________________________________________________________________________ 13 pin description (continued) pin name function 16 ccsu step-up converter compensation node. connect a series resistor-capacitor from this pin to gnd for compensating the converter control loop. this pin is actively driven to gnd in shutdown, overload, and thermal limit. see the step-up compensation section. 17 fbsu step-up converter feedback input. the feedback threshold is 1.25v. this pin is high impedance in shutdown. 18 onsu step-up converter on/off control. logic high = on. all other on_ pins are locked out until 1024 osc cycles after the step-up dc-to-dc converter output has reached its final value. this pin has an internal 330k ? pulldown resistance to gnd. 19 scf open-drain, active-low, short-circuit flag output. scf goes open when overload protection occurs and during startup. scf can drive high-side pfet switches connected to one or more outputs to completely disconnect the load when the channel turns off in response to a logic command or an overload. see the status outputs ( sdok , aux1ok , scf) section. 20 aux1ok open-drain, active-low, power-ok signal for aux1 controller. aux1ok goes low when the aux1 controller has successfully completed soft-start. aux1ok goes high impedance in shutdown, overload, and thermal limit. 21 sdok open-drain, active-low, power-ok signal for step-down converter. sdok goes low when the step- down has successfully completed soft-start. sdok goes high impedance in shutdown, overload, and thermal limit. 22 osc oscillator control. connect a timing capacitor from osc to gnd and a timing resistor from osc to pvsu (or other dc voltage) to set the oscillator frequency between 100khz and 1mhz. see the setting the switching frequency section. this pin is high impedance in shutdown. 23 pgsu power ground. connect all pg_ pins to gnd with short wide traces as close to the ic as possible. 24 lxsu step-up converter switching node. connect to the inductor of the step-up converter. lxsu is high impedance in shutdown. 25 pvsu power output of the step-up dc-to-dc converter. pvsu can also power other converter channels. connect pvsu and pv together. 26 pgm power ground. connect all pg_ pins to gnd with short wide traces as close to the ic as possible. 27 lxm main converter switching node. connect to the inductor of the main converter (can be configured as a step-up or step-down by susd). lxm is high impedance in shutdown. 28 pvm when susd = pvsu, the main converter is configured as a step-up and pvm is the main output. when susd = gnd, the main is configured as a step-down and pvm is the power input. 29 on2 aux2 controller on/off input. logic high = on; however, turn-on is locked out until 1024 osc cycles after the step-up has reached regulation. this pin has an internal 330k ? pulldown resistance to gnd. 30 cc2 aux2 controller compensation node. connect a series resistor-capacitor from this pin to gnd to compensate the converter control loop. this pin is actively driven to gnd in shutdown, overload, and thermal limit. see the aux compensation section.
max1566/max1567 six-channel, high-efficiency, digital camera power supplies 14 ______________________________________________________________________________________ pin name function max1566 (aux2 is configured as a boost): fb2 feedback threshold is 1.25v. 31 fb2 aux2 controller feedback input. this pin is high impedance in shutdown. max1567 (aux2 is configured as an inverter): fb2 feedback threshold is 0v. max1566 (aux2 is configured as a boost): connect indl2 to pvsu for optimum n-channel gate drive. 32 indl2 voltage input for aux2 gate driver. the voltage at indl2 sets the high gate-drive voltage. max1567 (aux2 is configured as an inverter): connect indl2 to the external p-channel mosfet source to ensure the p channel is completely off when dl2 swings high. 33 gnd analog ground. connect to all pg_ pins as close to the ic as possible. the max1566 configures dl2 to drive an n-channel fet in a boost configuration. dl2 is driven low in shutdown, overload, and thermal limit. 34 dl2 aux2 controller gate- drive output. dl2 drives between indl2 and gnd. the max1567 configures dl2 to drive a pfet in an inverter configuration. dl2 is driven high in shutdown, overload, and thermal limit. 35 dl3 aux3 controller gate-drive output. connect to the gate of an n-channel mosfet. dl3 drives between gnd and pvsu and supplies up to 500ma. this pin is actively driven to gnd in shutdown, overload, and thermal limit. 36 dl1 aux1 controller gate-drive output. connect to the gate of an n-channel mosfet. dl1 drives between gnd and pvsu and supplies up to 500ma. this pin is actively driven to gnd in shutdown, overload, and thermal limit. 37 pv ic power input. connect pvsu and pv together. 38 cc3 aux3 controller compensation node. connect a series resistor-capacitor from this pin to gnd for compensating the converter control loop. this pin is actively driven to gnd in shutdown, overload, and thermal limit. see the aux compensation section. 39 fb3l aux3 controller current-feedback input. connect a resistor from fb3l to gnd to set led current in led boost-drive circuits. the feedback threshold is 0.2v. connect this pin to gnd if using only the fb3h feedback. this pin is high impedance in shutdown. 40 on3 aux3 controller on/off input. logic high = on; however, turn-on is locked out until 1024 osc cycles after the step-up has reached regulation. this pin has an internal 330k ? pulldown resistance to gnd. pad ep exposed metal pad. this pad is connected to ground. note this internal connection is a soft-connect, meaning there is no internal metal or bond wire physically connecting the exposed pad to the gnd pin. the connection is through the silicon substrate of the die and then through a conductive epoxy. connecting the exposed pad to ground does not remove the requirement for a good ground connection to the appropriate pins. pin description (continued)
max1566/max1567 six-channel, high-efficiency, digital camera power supplies ______________________________________________________________________________________ 15 detailed description the max1566/max1567 include the following blocks to build a multiple-output digital camera power-supply system. both devices can accept inputs from a variety of sources including 1-cell li+ batteries, 2-cell alkaline or nimh batteries, and even systems designed to accept both battery types. the max1566/ max1567 include six dc-to-dc converter channels to generate all required voltages: step-up dc-to-dc converter (_su pins) with on-chip power fets main dc-to-dc converter (_m pins) with on-chip power fets that can be configured as either a step- up or step-down dc-to-dc converter step-down core dc-to-dc converter with on-chip mosfets (_sd pins) aux1 dc-to-dc controller for boost and flyback converters aux2 dc-to-dc controller for boost and flyback converters (max1566) aux2 dc-to-dc controller for inverting dc-to-dc converters (max1567) aux3 dc-to-dc controller for white led as well as conventional boost applications; includes open led overvoltage protection step-up dc-to-dc converter the step-up dc-to-dc switching converter typically is used to generate a 5v output voltage from a 1.5v to 4.5v battery input, but any voltage from v in to 5v can be set. an internal nfet switch and external synchro- nous rectifier allow conversion efficiencies as high as 95%. under moderate to heavy loading, the converter operates in a low-noise pwm mode with constant frequency and modulated pulse width. switching harmonics generated by fixed-frequency operation are consistent and easily filtered. efficiency is enhanced under light (<75ma typ) loading by an idle mode that switches the step-up only as needed to service the load. in this mode, the maximum inductor current is 150ma for each pulse. main dc-to-dc converter (step-up or step-down) the main converter can be configured as a step-up (figure 2) or a step-down converter (figure 1) with the susd pin. the main dc-to-dc converter is typically used to generate 3.3v, but any voltage from 2.7v to 5v can be set; however, the main output must not be set higher than the step-up output (pvsu). an internal mosfet switch and synchronous rectifier allow conversion efficiencies as high as 95%. under moderate to heavy loading, the converter operates in a low-noise pwm mode with constant frequency and modulated pulse width. switching harmonics generated by fixed-frequency operation are consistent and easily filtered. efficiency is enhanced under light loading (<150ma typical for step-up mode, <100ma typical for step-down mode) by assuming an idle mode during which the converter switches only as needed to service the load. step-down operation can be direct from a li+ cell if the minimum input voltage exceeds the desired output by approximately 200mv. note that if the main dc-to-dc, operating as a step-down, operates in dropout, the overload protection circuit senses an out-of-regulation condition and turns off all channels. li+ to 3.3v boost-buck operation when generating 3.3v from an li+ cell, boost-buck operation may be needed so a regulated output can be maintained for input voltages above and below 3.3v. in that case, it may be best to configure the main convert- er as a step-down (susd = gnd) and to connect its input, pvm, to the step-up output (pvsu), set to a volt- age at or above 4.2v (figures 1 and 3). the compound efficiency with this connection is typically up to 90%. this connection is also suitable for designs that must operate from both 1-cell li+ and 2 aa cells. note that the step-up output supplies both the step-up load and the main step-down input current when the main is powered from the step-up. the main input cur- rent reduces the available step-up output current for other loads. 2 aa to 3.3v operation in designs that operate only from 2 aa cells, the main dc-to-dc can be configured as a boost converter (susd = pvm) to maximize the 3.3v efficiency (figure 2).
max1566/max1567 six-channel, high-efficiency, digital camera power supplies 16 ______________________________________________________________________________________ v m +3.3v 200ma v sd +1.8v 350ma v su +5v 500ma v su to v batt dl1 fb1 dl2 fb2 fb3l pvm lxm fbm pvsd lxsd fbsd ref osc onsd on1 on3 (led) on2 ccsu ccsd ccm cc3 cc1 cc2 pgsd current- mode step- down pwm current- mode up or down pwm pvsu lxsu fbsu current- mode step-up pwm pv pgsu pgm outsu susd fb3h dl3 outsu scf aux1 pwm aux2 inverting pwm aux3 pwm ok pwr on or fault indl2 gnd onsu n1 l5 10 h l6 5.6 h l1 1.4 h d1 d2?5 leds -7.5v 40ma to ref v batt 15v 20ma to v batt to batt 1 li+ 2.8v to 4.2v c15 10 f c16 10 f c1 1 f r2 90.9k ? r1 1m ? r3 10 ? c2 0.1 f r4 47k ? c3 100pf c14 22 f r19 40.2k ? r20 90.9k ? c13 10 f c12 22 f c11 10 f r17 150k ? r18 90.9k ? l4 10 h c10 47 f r15 274k ? r16 90.9k ? d8 p1 l3 22 h d7 c17 1 f r14 90.9k ? r13 549k ? r11 1m ? r12 90.9k ? c18 1 f d6 l2 1.2 h n2 r5 r6 r7 r8 r9 r10 onm max1567 aux1ok sdok c4 c5 c6 c7 c8 c9 figure 1. typical 1-cell li+ powered system (3.3v logic is stepped down from +5v, and 1.8v core is stepped down directly from th e battery. alternate connections are shown in the following figures.)
max1566/max1567 six-channel, high-efficiency, digital camera power supplies ______________________________________________________________________________________ 17 v m +3.3v 500ma v sd +1.8v 250ma v su +5v 350ma v su to v su to v batt dl1 fb1 dl2 fb2 fb3l pvm lxm fbm pvsd lxsd fbsd ref osc onsd on1 on3 (led) on2 ccsu ccsd ccm cc3 cc1 cc2 pgsd current- mode step- down pwm current- mode up or down pwm pvsu lxsu fbsu current- mode step-up pwm pv pgsu pgm outsu susd fb3h dl3 outsu scf aux1 pwm aux2 inverting pwm aux3 pwm ok pwr on or fault indl2 gnd onsu n1 l5 3.3 h l6 10 h l1 1.4 h d1 d2?5 leds -7.5v 40ma to ref v batt 15v 20ma to v su to v m 2 aa 1.5v to 3.4v c15 10 f c16 10 f c1 1 f r2 90.9k ? r1 1m ? r3 10 ? c2 0.1 f r4 47k ? c3 100pf c14 47 f r19 40.2k ? r20 90.9k ? c13 10 f c21 47 f c11 10 f r17 150k ? r18 90.9k ? l4 4.7 h c10 47 f r15 274k ? r16 90.9k ? d8 p1 l3 22 h d7 c17 1 f r14 90.9k ? r13 549k ? r11 1m ? r12 90.9k ? c18 1 f d6 l2 1.2 h n2 r5 r6 r7 r8 r9 r10 onm max1567 to v batt aux1ok sdok c12 10 f c4 c5 c6 c7 c8 c9 figure 2. typical 2-cell aa-powered system (3.3v is boosted from the battery and 1.8v is stepped down from v m (3.3v).)
max1566/max1567 six-channel, high-efficiency, digital camera power supplies 18 ______________________________________________________________________________________ v m +3.3v 200ma v sd +1.8v 200ma v su +5v 100ma v su to v batt dl1 fb1 dl2 fb2 fb3l pvm lxm fbm pvsd lxsd fbsd ref osc onsd on1 on3 (led) on2 ccsu ccsd ccm cc3 cc1 cc2 pgsd current- mode step- down pwm current- mode up or down pwm pvsu lxsu fbsu current- mode step-up pwm pv pgsu pgm outsu susd fb3h dl3 outsu scf aux1 pwm aux2 inverting pwm aux3 pwm ok pwr on or fault indl2 gnd onsu n1 l5 10 h l6 10 h l1 1.4 h d1 d2?5 leds -7.5v 40ma to ref v batt 15v 20ma to v su to batt 2 aa or li+ 1.5v to 4.2v c15 10 f c16 10 f c1 1 f r2 90.9k ? r1 1m ? r3 10 ? c2 0.1 f r4 47k ? c3 100pf c14 22 f r19 40.2k ? r20 90.9k ? c13 10 f c12 22 f c11 10 f r17 150k ? r18 90.9k ? l4 4.7 h c10 47 f r15 274k ? r16 90.9k ? d8 p1 l3 22 h d7 c17 1 f r14 90.9k ? r13 549k ? r11 1m ? r12 90.9k ? c18 1 f d6 l2 1.2 h n2 r5 r6 r7 r8 r9 r10 onm max1567 aux1ok sdok c4 c5 c6 c7 c8 c9 figure 3. li+ or multibattery input (this power supply accepts inputs from 1.5v to 4.2v, so it can operate from either 2 aa cel ls or 1 li+ cell. the 3.3v logic supply and the 1.8v core supply are both stepped down from 5v for true boost-buck operation.)
max1566/max1567 six-channel, high-efficiency, digital camera power supplies ______________________________________________________________________________________ 19 2.35v v su onsu v ref 1v onsu refok die over temp f ault in clk normal mode startup oscillator internal power- ok 100,000- clock-cycle f ault timer ref to v ref 200ns one-shot soft-start ramp generator step-up soft-start timer done (sussd) 1.25v reference to internal power osc ccsu fbsu to v ref soft-start ramp generator ccsd fbsd onsd sussd on_ sussd to v ref soft-start ramp generator cc_ fb_ f ault current- mode dc-to-dc step-down f ault 1 of 3 voltage-mode dc-to-dc controllers aux_ pvsd lxsd ref gnd pv pgnd sdok dl_ fltall fltall f ault current- mode dc-to-dc step-up pvsu lxsu pgsu onsu fltall fltall f ault current- mode dc-to-dc step-down or step-up pvm susd lxm pgm soft-start ramp generator fbm to v ref clk sussd fltall onm aux1ok max1566 figure 4. max1566 functional diagram
max1566/max1567 six-channel, high-efficiency, digital camera power supplies 20 ______________________________________________________________________________________ core step-down dc-to-dc converter the step-down dc-to-dc is optimized for generating low output voltages (down to 1.25v) at high efficiency. the step-down runs from the voltage at pvsd. this pin can be connected directly to the battery if sufficient head- room exists to avoid dropout; otherwise, pvsd can be powered from the output of another converter. the step- down can also operate with the step-up, or the main con- verter in step-up mode, for boost-buck operation. under moderate to heavy loading, the converter oper- ates in a low-noise pwm mode with constant frequency and modulated pulse width. efficiency is enhanced under light (<75ma typ) loading by assuming an idle mode during which the step-down switches only as needed to service the load. in this mode, the maximum inductor current is 100ma for each pulse. the step- down dc-to-dc is inactive until the step-up dc-to-dc is in regulation. the step-down also features an open-drain sdok out- put that goes low when the step-down output is in regu- lation. sdok can be used to drive an external mosfet switch that gates 3.3v power to the processor after the core voltage is in regulation. this connection is shown in figure 15. aux1, aux2, and aux3 dc-to-dc controllers the three auxiliary controllers operate as fixed-frequen- cy voltage-mode pwm controllers. they do not have internal mosfets, so output power is determined by external components. the controllers regulate output voltage by modulating the pulse width of the dl_ drive signal to an external mosfet switch. on the max1566, aux1 and aux2 are boost/flyback pwm controllers. on the max1567, aux1 is a boost/fly- back pwm controller, but aux2 is an inverting pwm controller. on both devices, aux3 is a boost/flyback controller that can be connected to regulate output volt- age and/or current (for white-led drive). figure 5 shows a functional diagram of an aux boost controller channel. a sawtooth oscillator signal at osc governs timing. at the start of each cycle, dl_ goes high, turning on the external nfet switch. the switch then turns off when the internally level-shifted sawtooth rises above cc_ or when the maximum duty cycle is exceed- ed. the switch remains off until the start of the next cycle. a transconductance error amplifier forms an integrator at cc_ to maintain high dc loop gain and accuracy. the auxiliary controllers do not start until 1024 osc cycles after the step-up dc-to-dc output is in regula- tion. if the auxiliary controller remains faulted for 100,000 osc cycles (200ms at 500khz), then all max1566/max1567 channels latch off. maximum duty cycle the aux pwm controllers have a guaranteed maximum duty cycle of 80%: all controllers can achieve at least 80% and typically reach 85%. in boost designs that employ continuous current, the maximum duty cycle limits the boost ratio so: 1 - v in / v out < 80% with discontinuous inductor current, no such limit exists for the input/output ratio since the inductor has time to fully discharge before the next cycle begins. aux1 aux1 can be used for conventional dc-to-dc boost and flyback designs (figures 8 and 9). its output (dl1) is designed to drive an n-channel mosfet. its feed- back (fb1) threshold is 1.25v. aux2 in the max1566, aux2 is identical to aux1. in the max1567, aux2 is an inverting controller that gener- ates a regulated negative output voltage, typically for ccd and lcd bias. this is useful in height-limited designs where transformers may not be desired. the aux2 mosfet driver (dl2) in the max1567 is designed to drive p-channel mosfets. indl2 biases the driver so v indl2 is the high output level of dl2. indl2 should be connected to the p-channel mosfet source to ensure the mosfet turns completely off when dl2 is high. see figure 10 for a typical inverter circuit. aux3 dc-to-dc controller, led driver the aux3 step-up dc-to-dc controller has two feed- back inputs, fb3l and fb3h, with feedback thresholds of 0.2v (fb3l) and 1.25v (fb3h). if used as a conven- tional voltage-output step-up, fb3l is grounded and fb3h is used as the feedback input. in that case, aux3 behaves exactly like aux1. if aux3 is used as a switch-mode boost current source for white leds, fb3l provides current-sensing feed- back, while fb3h provides (optional) open-led over- voltage protection (figure 7).
max1566/max1567 six-channel, high-efficiency, digital camera power supplies ______________________________________________________________________________________ 21 level shift soft-start f ault protection max1567 aux2 inverter enable dl_ clk refi 0.85 ref cc2 fb2 ref osc r s q level shift soft-start f ault protection max1566 (aux1/aux2) max1567 (aux1) enable dl_ clk refi 0.85 ref cc fb ref osc r s q in 1024 clock cycles, soft-start ramps up refi from 0v to v ref in max1566/max1567 aux_ boost controllers and ramps down refi from v ref to 0v in max1567 aux2 inverter. figure 5. aux controller functional diagram
max1566/max1567 six-channel, high-efficiency, digital camera power supplies 22 ______________________________________________________________________________________ master-slave configurations the max1566/max1567 support max1801 slave pwm controllers that obtain input power, a voltage reference, and an oscillator signal directly from the max1566/ max1567 master. the master-slave configuration allows channels to be easily added and minimizes system cost by eliminating redundant circuitry. the slaves also con- trol the harmonic content of noise because their operat- ing frequency is synchronized to that of the max1566/ max1567 master converter. a max1801 connection to the max1566/max1567 is shown in figure 14. status outputs ( sdok , aux1ok , scf) the max1566/max1567 include three versatile status outputs that can provide information to the system. all are open-drain outputs and can directly drive mosfet switches to facilitate sequencing, disconnect loads during overloads, or perform other hardware-based functions. c osc v ref (1.25v) v su r osc osc 200ns one-shot max1566 max1567 figure 6. oscillator functional diagram fb3l (0.2v) fb3h (1.25v) dl3 pvsu aux3 pwm d2?5 leds r2 r1 r3 max1566 max1567 (partial) to v batt note: if open led protection is not required, remove r2 and r1 and ground fb3h. figure 7. led drive with open led overvoltage protection is provided by the additional feedback input to aux3, fb3h. dl_ fb_ pvsu aux pwm +15v 50ma lcd d6 q1 to v batt max1566 max1567 (partial) note: this circuit can operate with aux1, aux2, or aux3 on the max1566, and with aux1 or aux3 on the max1567. to use aux3, fb3l = gnd, and fb3h is used for feedback. figure 8. +15v lcd bias with basic boost topology dl_ fb_ pvsu aux pwm +15v 50ma ccd+ -7.5v 30ma ccd- d2 q1 to v batt max1566 max1567 (partial) note: this circuit can operate with aux1, aux2, or aux3 on the max1566, and with aux1 or aux3 on the max1567. to use aux3, fb3l = gnd, and fb3h is used for feedback. figure 9. +15v and -7.5v ccd bias with transformer
max1566/max1567 six-channel, high-efficiency, digital camera power supplies ______________________________________________________________________________________ 23 sdok pulls low when the step-down has successfully completed soft-start. sdok goes high impedance in shutdown, overload, and thermal limit. a typical use for sdok is to drive a p-channel mosfet that connects 3.3v power to the cpu i/o after the cpu core is pow- ered up (figure 15), thus providing safe sequencing in hardware without system intervention. a a u u x x 1 1 o o k k pulls low when the aux1 controller has suc- cessfully completed soft-start. aux1ok goes high impedance in shutdown, overload, and thermal limit. a typical use for aux1ok is to drive a p-channel mosfet that connects 5v power to the ccd after the 15v ccd bias (generated by aux1) is powered up (figure 16). scf goes high (high impedance, open drain) when overload protection occurs. under normal operation, scf pulls low. scf can drive a high-side p-channel mosfet switch that can disconnect a load during power-up or when a channel turns off in response to a logic command or an overload. several connections are possible for scf. one is shown in figure 17 where scf provides load disconnect for the step-up on fault and power-up. dl2 fb2 ref aux2 inverting pwm indl2 -7.5v 100ma to v batt r top r ref max1567 (partial) figure 10. regulated -7.5v negative ccd (bias is provided by conventional inverter (works only with the max1567).) max1566 max1567 (partial) aux_ pwm pvsu dl_ fb_ c2 1 f to v batt 1 f l1 10 h d2 r1 1m ? r2 90.9k ? c1 1 f d3 d1 q1 c3 1 f v out+ +15v 20ma v out- -15v 10ma figure 11. ?5v output using an aux-driven boost with charge-pump inversion max1566/max1567 (partial) aux_ pwm pvsu dl_ fb_ to v batt max1616 fb_ gnd shdn in out +1.25v +15v 20ma -7.5v 20ma note: this circuit can operate with aux1, aux2, or aux3 on the max1566, and with aux1 or aux3 on the max1567. to use aux3, fb3l = gnd, and fb3h is used for feedback. figure 12. +15v and -7.5v ccd bias without transformer using boost with a diode-capacitor charge pump (a positive- output linear regulator (max1616) can be used to regulate the negative output of the charge pump.)
max1566/max1567 six-channel, high-efficiency, digital camera power supplies 24 ______________________________________________________________________________________ current- mode up or down pwm pvm lxm l3 pgm max1566 max1567 (partial) fbm susd sdok 3.3v to cpu v m +3.3v to v batt current- mode step- down pwm pvsd lxsd l4 pgsd fbsd v sd +1.8v 350ma figure 15. using sdok to drive external pfet that gates 3.3v power to cpu after 1.8v core voltage is in regulation max1566 max1567 (partial) max1801 to batt dl fb comp gnd ref osc in dcon pvsu osc ref v out figure 14. adding a pwm channel with an external max1801 slave controller q1 c2 d1 r1 output 3.3v l1 r2 v su pv pvsu part of max1566 max1567 (partial) dl_ fb_ input 1-cell li+ l2 figure 13. sepic converter additional boost-buck channel
max1566/max1567 six-channel, high-efficiency, digital camera power supplies ______________________________________________________________________________________ 25 soft-start the max1566/max1567 channels feature a soft-start function that limits inrush current and prevents exces- sive battery loading at startup by ramping the output voltage of each channel up to the regulation voltage. this is accomplished by ramping the internal reference inputs to each channel error amplifier from 0v to the 1.25v reference voltage over a period of 4096 oscillator cycles (16ms at 500khz) when initial power is applied or when a channel is enabled. the step-down soft-start ramp takes half the time (2048 clock cycles) of the other channel ramps. this allows the step-down and main outputs to track each other and rise at nearly the same dv/dt rate on power-up. once the step-down output reaches its regulation point (1.5v or 1.8v typ), the main output (3.3v typ) continues to rise at the same ramp rate. see the typical operating characteristics main and step-down startup waveforms graphs. soft-start is not included in the step-up converter to avoid limiting startup capability with loading. fault protection the max1566/max1567 have robust fault and overload protection. after power-up, the device is set to detect an out-of-regulation state that could be caused by an overload or short. if any dc-to-dc converter channel (step-up, main, step-down, or any of the auxiliary con- trollers) remains faulted for 100,000 clock cycles (200ms at 500khz), then all outputs latch off until the step-up dc-to-dc converter is reinitialized by the onsu pin or by cycling the input power. the fault- detection circuitry for any channel is disabled during its initial turn-on soft-start sequence. an exception to the standard fault behavior is that there is no 100,000 clock cycle delay in entering the fault state if the step-up output (pvsu) is dragged below its 2.5v uvlo threshold or is shorted. in this case, the max1566 max1567 (partial) aux1ok current- mode step-up pwm pvsu pv lxsu l2 pgsu fbsu v su +5v gated +5v to ccd to v batt to v batt dl1 fb1 pvsu aux1 pwm 15v 100ma d6 figure 16. aux1ok drives an external pfet that gates 5v supply to the ccd after the +15v ccd bias supply is up
max1566/max1567 six-channel, high-efficiency, digital camera power supplies 26 ______________________________________________________________________________________ step-up uvlo immediately triggers and shuts down all channels. the step-up then continues to attempt start- ing. if the step-up output short remains, these attempts cannot succeed since pvsu remains near ground. if a soft-short or overload remains on pvsu, the startup oscillator switches the internal n-channel mosfet, but fault is retriggered if regulation is not achieved by the end of the soft-start interval. if pvsu is dragged below the input, the overload is supplied by the body diode of the internal synchronous rectifier, or by a schottky diode connected from the battery to pvsu. if desired, this overload current can be interrupted by a p-channel mosfet controlled by scf, as shown in figure 17. reference the max1566/max1567 has a precise 1.250v refer- ence. connect a 0.1? ceramic bypass capacitor from ref to gnd within 0.2in (5mm) of the ref pin. ref can source up to 200? and is enabled whenever onsu is high and pvsu is above 2.5v. the auxiliary controllers and max1801 slave controllers (if connected) each sink up to 30? ref current during startup. in addition, the feedback network for the aux2 inverter (max1567) also draws current from ref. if the 200? ref load limit must be exceeded, buffer ref with an external op amp. oscillator all dc-to-dc converter channels employ fixed-frequency pwm operation. the operating frequency is set by an rc network at the osc pin. the range of usable settings is 100khz to 1mhz. when max1801 slave controllers are added, they operate at the frequency set by osc. the oscillator uses a comparator, a 200ns one-shot, and an internal nfet switch in conjunction with an external timing resistor and capacitor (figure 6). when the switch is open, the capacitor voltage exponentially approaches the step-up output voltage from zero with a time constant given by the product of r osc and c osc . the compara- tor output switches high when the capacitor voltage reaches v ref (1.25v). in turn, the one-shot activates the internal mosfet switch to discharge the capacitor for 200ns, and the cycle repeats. the oscillation frequency changes as the main output voltage ramps upward fol- lowing startup. the oscillation frequency is then constant once the main output is in regulation. low-voltage startup oscillator the max1566/max1567 internal control and reference- voltage circuitry receive power from pvsu and do not function when pvsu is less than 2.5v. to ensure low- voltage startup, the step-up employs a low-voltage startup oscillator that activates at 0.9v if a schottky rec- tifier is connected from v batt to pvsu (1.1v with no schottky rectifier). the startup oscillator drives the inter- nal n-channel mosfet at lxsu until pvsu reaches 2.5v, at which point voltage control is passed to the current-mode pwm circuitry. once in regulation, the max1566/max1567 operate with inputs as low as 0.7v since internal power for the ic is supplied by pvsu. at low input voltages, the step- current-mode step-up pwm pvsu pv lxsu l2 pgsu max1566 max1567 (partial) fbsd scf ok pwr on or fault v su +5v to v batt figure 17. scf drives pfet load switch on 5v to disconnect load on fault and allow full-load startup current-mode step-down pvsd lxsd 4.7 h 22 f 10 f pgsd max1566 max1567 (partial) pvsu pv r1 56k ? r3 100k ? r2 100k ? fbsd v fbsd 1.25v v su 3.3v v sd 0.8v figure 18. setting pvsd for outputs below 1.25v
max1566/max1567 six-channel, high-efficiency, digital camera power supplies ______________________________________________________________________________________ 27 up may have difficulty starting into heavy loads (see the minimum startup voltage vs. load current (outsu) graph in the typical operating characteristics ); however, this can be remedied by connecting an external p- channel load switch driven by scf so the load is not connected until the pvsu is in regulation (figure 17). shutdown the step-up converter is activated with a high input at onsu. the main converter (step-up or step-down) is acti- vated by a high input on onm. the step-down and auxil- iary dc-to-dc converters 1, 2, and 3 activate with high inputs at onsd, on1, on2, and on3, respectively. the step-down, main, and aux_ converters cannot be activat- ed until pvsu is in regulation. for automatic startup, con- nect on_ to pvsu or a logic level greater than 1.6v. design procedure setting the switching frequency choose a switching frequency to optimize external component size or circuit efficiency for the particular application. typically, switching frequencies between 400khz and 500khz offer a good balance between component size and circuit efficiency?igher frequen- cies generally allow smaller components, and lower fre- quencies give better conversion efficiency. the switching frequency is set with an external timing resis- tor (r osc ) and capacitor (c osc ). at the beginning of a cycle, the timing capacitor charges through the resistor until it reaches v ref . the charge time, t 1 , is as follows: t 1 = -r osc x (c osc + c par ) x ln (1 - 1.25 / v pvsu ) where c par (15pf typ) is the parasitic capacitance at the osc pin due to internal esd protection structure and the die-to-package capacitance. the internal comparator that compares the capacitor c osc voltage to the reference has a delay t d of 50ns (typ). the capacitor voltage then decays to zero over time, t 2 = 200ns. the oscillator frequency is as follows: f osc = 1 / (t 1 + t d + t 2 ) f osc can be set from 100khz to 1mhz. choose c osc between 22pf and 470pf. determine r osc : r osc = (200ns + 50ns - 1/ f osc ) / ([c osc + c par ] ln[1 - 1.25 / v pvsu ]) see the typical operating characteristics for f osc vs. r osc using different values of c osc . setting output voltages all max1566/max1567 output voltages are resistor set. the fb_ threshold is 1.25v for all channels except for fb3l (0.2v) on both devices and fb2 (inverter) on the max1567. when setting the voltage for any channel except the max1567 aux2, connect a resistive volt- age-divider from the channel output to the correspond- ing fb_ input and then to gnd. the fb_ input bias current is less than 100na, so choose the bottom-side (fb_-to-gnd) resistor to be 100k ? or less. then calcu- late the top-side (output-to-fb_) resistor: r top = r bottom [(v out / 1.25) - 1] when using aux3 to drive white leds (figure 7), select the led current-setting resistor (r3, figure 7) using the following formula: r3 = 0.2v / i led the fb2 threshold on the max1567 is 0v. to set the aux2 negative output voltage, connect a resistive volt- age-divider from the negative output to the fb2 input, and then to ref. the fb2 input bias current is less than 100na, so choose the ref-side (fb2-to-ref) resistor (r ref ) to be 100k ? or less. then calculate the top-side (output-to-fb2) resistor: r top = r ref (-v out(aux2) / 1.25) general filter capacitor selection the input capacitor in a dc-to-dc converter reduces current peaks drawn from the battery or other input power source and reduces switching noise in the con- troller. the impedance of the input capacitor at the switching frequency should be less than that of the input source so high-frequency switching currents do not pass through the input source. the output capacitor keeps output ripple small and ensures control-loop stability. the output capacitor must also have low impedance at the switching frequency. ceramic, polymer, and tantalum capacitors are suitable, with ceramic exhibiting the lowest esr and high-frequen- cy impedance. output ripple with a ceramic output capacitor is approximately as follows: v ripple = i l(peak) [1 / (2 x f osc x c out )] if the capacitor has significant esr, the output ripple component due to capacitor esr is as follows: v ripple(esr) = i l(peak) x esr output capacitor specifics are also discussed in each converter? compensation section. step-up component selection this section describes component selection for the step-up, as well as for the main, if susd = pv. the external components required for the step-up are an inductor, an input and output filter capacitor, and a compensation rc.
max1566/max1567 six-channel, high-efficiency, digital camera power supplies 28 ______________________________________________________________________________________ the inductor is typically selected to operate with contin- uous current for best efficiency. an exception might be if the step-up ratio, (v out / v in ), is greater than 1 / (1 - d max ), where d max is the maximum pwm duty factor of 80%. when using the step-up channel to boost from a low input voltage, loaded startup is aided by connecting a schottky diode from the battery to pvsu. see the minimum startup voltage vs. load current graph in the typical operating characteristics . step-up inductor in most step-up designs, a reasonable inductor value (l ideal ) can be derived from the following equation, which sets continuous peak-to-peak inductor current at 1/2 the dc inductor current: l ideal = [2v in(max) x d(1 - d)] / (i out x f osc ) where d is the duty factor given by: d = 1 - (v in / v out ) given l ideal , the consistent peak-to-peak inductor cur- rent is 0.5 i out / (1 - d). the peak inductor current, i ind(pk) = 1.25 i out / (1 - d). inductance values smaller than l ideal can be used to reduce inductor size; however, if much smaller values are used, inductor current rises and a larger output capacitance may be required to suppress output ripple. step-up compensation the inductor and output capacitor are usually chosen first in consideration of performance, size, and cost. the compensation resistor and capacitor are then chosen to optimize control-loop stability. in some cases, it may help to readjust the inductor or output-capacitor value to get optimum results. for typical designs, the component values in the circuit of figure 1 yield good results. the step-up converter employs current-mode control, thereby simplifying the control-loop compensation. when the converter operates with continuous inductor current (typically the case), a right-half-plane zero appears in the loop-gain frequency response. to ensure stability, the control-loop gain should cross over (drop below unity gain) at a frequency (f c ) much less than that of the right-half-plane zero. the relevant characteristics for step-up channel com- pensation are as follows: transconductance (from fb to cc), gm ea (135?) current-sense amplifier transresistance, r cs (0.3v/a) feedback regulation voltage, v fb (1.25v) step-up output voltage, v su , in v output load equivalent resistance, r load , in ? = v out / i load the key steps for step-up compensation are as follows: 1) place f c sufficiently below the right-half-plane zero (rhpz) and calculate c c . 2) select r c based on the allowed load-step transient. r c sets a voltage delta on the c c pin that corre- sponds to load-current step. 3) calculate the output-filter capacitor (c out ) required to allow the r c and c c selected. 4) determine if c p is required (if calculated to be >10pf). for continuous conduction, the right-half-plane zero fre- quency (f rhpz ) is given by the following: f rhpz = v out (1 - d) 2 / (2 x l x i load ) where d = the duty cycle = 1 - (v in / v out ), l is the inductor value, and i load is the maximum output cur- rent. typically target crossover (f c ) for 1/6 of the rhpz. for example, if we assume f osc = 500khz, v in = 2.5v, v out = 5v, and i out = 0.5a, then r load = 10 ? . if we select l = 4.7?, then: f rhpz = 5 (2.5 / 5) 2 / (2 x 4.7 x 10 -6 x 0.5) = 84.65khz choose f c = 14khz. calculate c c : c c = (v fb / v out )(r load / r cs )(gm / 2 x f c )(1 - d) = (1.25 / 5)(10 / 0.3) x [135? / (6.28 x 14khz)] (2/5) = 6.4nf choose 6.8nf. now select r c so transient-droop requirements are met. as an example, if 4% transient droop is allowed, the input to the error amplifier moves 0.04 x 1.25v, or 50mv. the error-amp output drives 50mv x 135?, or 6.75?, across r c to provide transient gain. since the current-sense transresistance is 0.3v/a, the value of r c that allows the required load-step swing is as follows: r c = 0.3 i ind(pk) / 6.75? in a step-up dc-to-dc converter, if l ideal is used, out- put current relates to inductor current by: i ind(pk) = 1.25 i out / (1 - d) = 1.25 i out x v out / v in so, for a 500ma output load step with v in = 2.5v and v out = 5v: r c = [1.25(0.3 x 0.5 x 5) / 2)] / 6.75? = 69.4k ? note that the inductor does not limit the response in this case since it can ramp at 2.5v / 4.7?, or 530ma/?. the output filter capacitor is then chosen so the c out r load pole cancels the r c c c zero: c out x r load = r c x c c
max1566/max1567 six-channel, high-efficiency, digital camera power supplies ______________________________________________________________________________________ 29 for the example: c out = 68k ? x 6.8nf / 10 ? = 46? choose 47? for c out . if the available c out is sub- stantially different from the calculated value, insert the available c out value into the above equation and recalculate r c . higher substituted c out values allow a higher r c , which provides higher transient gain and consequently less transient droop. if the output filter capacitor has significant esr, a zero occurs at the following: z esr = 1 / (2 x c out x r esr ) if z esr > f c , it can be ignored, as is typically the case with ceramic output capacitors. if z esr is less than f c , it should be cancelled with a pole set by capacitor c p connected from cc to gnd: c p = c out x r esr / r c if c p is calculated to be <10pf, it can be omitted. step-down component selection this section describes component selection for the step-down converter, and for the main converter if used in step-down mode (susd = gnd). step-down inductor the external components required for the step-down are an inductor, input and output filter capacitors, and compensation rc network. the max1566/max1567 step-down converter provides best efficiency with continuous inductor current. a rea- sonable inductor value (l ideal ) can be derived from the following: l ideal = [2(v in ) x d(1 - d)] / i out x f osc this sets the peak-to-peak inductor current at 1/2 the dc inductor current. d is the duty cycle: d = v out / v in given l ideal , the peak-to-peak inductor current is 0.5 i out . the absolute-peak inductor current is 1.25 i out . inductance values smaller than l ideal can be used to reduce inductor size; however, if much smaller values are used, inductor current rises, and a larger output capaci- tance may be required to suppress output ripple. larger values than l ideal can be used to obtain higher output current, but typically with larger inductor size. step-down compensation the relevant characteristics for step-down compensa- tion are as follows: transconductance (from fb to c c ), gm ea (135?) step-down slope-compensation pole, p slope = v in / ( l) current-sense amplifier transresistance, r cs (0.6v/a) feedback-regulation voltage, v fb (1.25v) step-down output voltage, v sd , in v output-load equivalent resistance, r load , in ? = v out / i load the key steps for step-down compensation are as follows: 1) set the compensation rc to zero to cancel the r load c out pole. 2) set the loop crossover below the lower of 1/5 the slope compensation pole or 1/5 the switching frequency. if we assume v in = 2.5v, v out = 1.8v, and i out = 350ma, then r load = 5.14 ? . if we select f osc = 500khz and l = 5.6?. p slope = v in / ( l) = 142khz, so choose f c = 24khz and calculate c c : c c = (v fb / v out )(r load / r cs )(gm / 2 x f c ) = (1.25 / 1.8)(5.14 / 0.6) x [135? / (6.28 x 24khz)] = 6.4nf choose 6.8nf. now select r c so transient-droop requirements are met. as an example, if 4% transient droop is allowed, the input to the error amplifier moves 0.04 x 1.25v, or 50mv. the error-amp output drives 50mv x 135?, or 6.75? across r c to provide transient gain. since the current-sense transresistance is 0.6v/a, the value of r c that allows the required load-step swing is as follows: r c = 0.6 i ind(pk) / 6.75? in a step-down dc-to-dc converter, if l ideal is used, output current relates to inductor current by the following: i ind(pk) = 1.25 i out so for a 250ma output load step with v in = 2.5v and v out = 1.8v: r c = (1.25 x 0.6 x 0.25) / 6.75? = 27.8k ? choose 27k ? . note that the inductor does somewhat limit the response in this case since it ramps at (v in - v out ) / 5.6?, or (2.5 - 1.8) / 5.6? = 125ma/?. the output filter capacitor is then chosen so the c out r load pole cancels the r c c c zero: c out x r load = r c x c c
max1566/max1567 six-channel, high-efficiency, digital camera power supplies 30 ______________________________________________________________________________________ for the example: c out = 27k ? x 6.8nf / 5.14 ? = 35.7? since ceramic capacitors are common in either 22? or 47? values, 22? is within a factor of two of the ideal value and still provides adequate phase margin for stability. if the output filter capacitor has significant esr, a zero occurs at the following: z esr = 1 / (2 x c out x r esr ) if z esr > f c , it can be ignored, as is typically the case with ceramic output capacitors. if z esr < f c , it should be cancelled with a pole set by capacitor c p connect- ed from c c to gnd: c p = c out x r esr / r c if c p is calculated to be <10pf, it can be omitted. aux controller component selection external mosfet all max1566/max1567 aux controllers drive external logic-level mosfets. significant mosfet selection parameters are as follows: on-resistance (r ds(on) ) maximum drain-to-source voltage (v ds(max) ) total gate charge (q g ) reverse transfer capacitance (c rss ) on the max1566, all aux drivers are designed for n- channel mosfets. on the max1567, aux2 is a dc-to- dc inverter, so dl2 is designed to drive a p-channel mosfet. in both devices, the driver outputs dl1 and dl3 swing between pvsu and gnd. mosfet driver dl2 swings between indl2 and gnd. use a mosfet with on-resistance specified with gate drive at or below the main output voltage. the gate charge, q g , includes all capacitance associated with charging the gate and helps to predict mosfet transi- tion time between on and off states. mosfet power dissipation is a combination of on-resistance and tran- sition losses. the on-resistance loss is as follows: p rdson = d x i l 2 x r ds(on) where d is the duty cycle, i l is the average inductor current, and r ds(on) is mosfet on-resistance. the transition loss is approximately as follows: p trans = (v out x i l x f osc x t t ) / 3 where v out is the output voltage, i l is the average inductor current, f osc is the switching frequency, and t t is the transition time. the transition time is approxi- mately q g / i g , where q g is the total gate charge, and i g is the gate-drive current (0.5a typ). the total power dissipation in the mosfet is as follows: p mosfet = p rdson + p trans diode for most aux applications, a schottky diode rectifies the output voltage. schottky low forward voltage and fast recovery time provide the best performance in most applications. silicon signal diodes (such as 1n4148) are sometimes adequate in low-current (<10ma), high-voltage (>10v) output circuits where the output voltage is large compared to the diode forward voltage. aux compensation the auxiliary controllers employ voltage-mode control to regulate their output voltage. optimum compensa- tion depends on whether the design uses continuous or discontinuous inductor current. aux step-up, discontinuous inductor current when the inductor current falls to zero on each switch- ing cycle, it is described as discontinuous . the inductor is not utilized as efficiently as with continuous current, but in light-load applications this often has little negative impact since the coil losses may already be low com- pared to other losses. a benefit of discontinuous induc- tor current is more flexible loop compensation, and no maximum duty-cycle restriction on boost ratio. to ensure discontinuous operation, the inductor must have a sufficiently low inductance to fully discharge on each cycle. this occurs when: l < [v in 2 (v out - v in ) / v out 3 ] [r load / (2f osc )] a discontinuous current boost has a single pole at the following: f p = (2v out - v in ) / (2 x r load x c out x v out ) choose the integrator cap so the unity-gain crossover, f c , occurs at f osc / 10 or lower. note that for many aux circuits, such as those powering motors, leds, or other loads that do not require fast transient response, it is often acceptable to overcompensate by setting f c at f osc / 20 or lower. c c is then determined by the following: c c = [2v out x v in / ((2v out - v in ) x v ramp )] [v out / (k(v out - v in ))] 1/2 [(v fb / v out )(g m / (2 x f c ))] where: k = 2l x f osc / r load and v ramp is the internal slope-compensation voltage ramp of 1.25v.
max1566/max1567 six-channel, high-efficiency, digital camera power supplies ______________________________________________________________________________________ 31 the c c r c zero is then used to cancel the f p pole, so: r c = r load x c out x v out / [(2v out - v in ) x c c ] aux step-up, continuous inductor current continuous inductor current can sometimes improve boost efficiency by lowering the ratio between peak inductor current and output current. it does this at the expense of a larger inductance value that requires larger size for a given current rating. with continuous inductor- current boost operation, there is a right-half-plane zero, z rhp , at the following: z rhp = (1 - d) 2 x r load / (2 x l) where (1 - d) = v in / v out (in a boost converter). there is a complex pole pair at the following: f 0 = v out / [2 x v in (l x c out ) 1/2 ] if the zero due to the output capacitance and esr is less than 1/10 the right-half-plane zero: z cout = 1 / (2 x c out x r esr ) < z rhp / 10 then choose c c so the crossover frequency f c occurs at z cout . the esr zero provides a phase boost at crossover: c c = (v in / v ramp ) (v fb / v out ) [g m / (2 x z cout )] choose r c to place the integrator zero, 1 / (2 x r c x c c ), at f 0 to cancel one of the pole pairs: r c = v in (l x c out ) 1/2 / (v out x c c ) if z cout is not less than z rhp / 10 (as is typical with ceramic output capacitors) and continuous conduction is required, then cross the loop over before z rhp and f 0 : f c < f 0 / 10, and f c < z rhp / 10 in that case: c c = (v in / v ramp ) (v fb / v out ) (g m / (2 x f c )) place: 1 / (2 x r c x c c ) = 1 / (2 x r load x c out ), so that r c = r load x c out / c c or, reduce the inductor value for discontinuous operation. max1567 aux2 inverter compensation, discontinuous inductor current if the load current is very low ( 40ma), discontinuous current is preferred for simple loop compensation and freedom from duty-cycle restrictions on the inverter input-output ratio. to ensure discontinuous operation, the inductor must have a sufficiently low inductance to fully discharge on each cycle. this occurs when: l < [v in / (|v out | + v in )] 2 r load / (2f osc ) a discontinuous current inverter has a single pole at the following: f p = 2 / (2 x r load x c out ) choose the integrator cap so the unity-gain crossover, f c , occurs at f osc / 10 or lower. note that for many aux circuits that do not require fast transient response, it is often acceptable to overcompensate by setting f c at f osc / 20 or lower. c c is then determined by the following: c c = [v in / (k 1/2 x v ramp )] [v ref / (v out + v ref )] [g m / (2 x f c )] where k = 2l x f osc / r load , and v ramp is the internal slope-compensation voltage ramp of 1.25v. the c c r c zero is then used to cancel the f p pole, so: r c = (r load x c out ) / (2c c ) max1567 aux2 inverter compensation, continuous inductor current continuous inductor current may be more suitable for larger load currents (50ma or more). it improves effi- ciency by lowering the ratio between peak inductor cur- rent and output current. it does this at the expense of a larger inductance value that requires larger size for a given current rating. with continuous inductor-current inverter operation, there is a right-half-plane zero, z rhp , at: z rhp = [(1 - d) 2 / d] x r load / (2 x l) where d = |v out | / (|v out | + v in ) (in an inverter). there is a complex pole pair at: f 0 = (1 - d) / (2 (l x c) 1/2 ) if the zero due to the output-capacitor capacitance and esr is less than 1/10 the right-half-plane zero: z cout = 1 / (2 x c out x r esr ) < z rhp / 10 then choose c c such that the crossover frequency f c occurs at z cout . the esr zero provides a phase boost at crossover: c c = (v in / v ramp ) [v ref / (v ref + |v out |)] [g m / (2 x z cout )] choose r c to place the integrator zero, 1 / (2 x r c x c c ), at f 0 to cancel one of the pole pairs: r c = (l x c out ) 1/2 / [(1 - d) x c c ] if z cout is not less than z rhp / 10 (as is typical with ceramic output capacitors) and continuous conduction is required, then cross the loop over before z rhp and f 0 : f c < f 0 /10, and f c < z rhp / 10
max1566/max1567 six-channel, high-efficiency, digital camera power supplies 32 ______________________________________________________________________________________ in that case: c c = (v in / v ramp ) [v ref / (v ref + |v out |)] [g m / (2 x f c )] place: 1 / (2 x r c x c c ) = 1 / (2 x r load x c out ), so that r c = r load x c out / c c or, reduce the inductor value for discontinuous operation. applications information typical operating circuits figures 1, 2, and 3 show connections for aa and li+ battery arrangements. figures 7?3 show various con- nections for the aux1, 2, and 3 controllers. figures 15, 16, and 17 show various connections for the sdok , aux1ok , and scf outputs. figure 1. typical operating circuit for one li+ cell in this connection, the main converter is operated as a step-down (susd = gnd) and is powered from pvsu. this provides boost-buck operation for the main 3.3v output so a regulated output is maintained over the li+ 2.7v to 4.2v cell voltage range. the compound efficien- cy from the battery to the 3.3v output reaches 90%. the step-down 1.8v (core) output is powered directly from v batt . the ccd and lcd voltages are generated with a trans- formerless design. aux1 generates +15v for ccd posi- tive and lcd bias. the max1567 aux2 inverter generates -7.5v for negative ccd bias. the aux3 con- troller generates a regulated current for a series net- work of four white leds that backlight the lcd. figure 2. typical operating circuit for 2 aa cells figure 2 is optimized for 2-cell aa inputs (1.5v to 3.7v) by connecting the step-down input (pvsd) to the main output (pvm). the main 3.3v output operates directly from the battery as a step-up (susd = pvsd). the 1.8v core output now operates as a boost-buck with efficien- cy up to 90%. the rest of the circuit is unchanged from figure 1. figure 3. typical operating circuit for 2 aa cells and 1-cell li+ the max1566/max1567 can also allow either 1-cell li+ or 2 aa cells to power the same design. if the step- down and main inputs are both connected to pvsu, then both the 3.3v and 1.8v outputs operate as boost- buck converters. there is an efficiency penalty com- pared to stepping down vsd directly from the battery, but that is not possible with a 1.5v input. furthermore, the cascaded boost-buck efficiency com- pares favorably with other boost-buck techniques. led, lcd, and other boost applications any aux channel (except for the aux2 inverter on the max1567) can be used for a wide variety of step-up applications. these include generating 5v or some other voltage for motor or actuator drive, generating 15v or a similar voltage for lcd bias, or generating a step-up current source to efficiently drive a series array of white leds to display backlighting. figures 7 and 8 show examples of these applications. multiple-output flyback circuits some applications require multiple voltages from a sin- gle converter channel. this is often the case when gen- erating voltages for ccd bias or lcd power. figure 9 shows a two-output flyback configuration with an aux channel. the controller drives an external mosfet that switches the transformer primary. two transformer sec- ondaries generate the output voltages. only one posi- tive output voltage can be fed back, so the other voltages are set by the turns-ratio of the transformer secondaries. the load stability of the other secondary voltages depends on transformer leakage inductance and winding resistance. voltage regulation is best when the load on the secondary that is not fed back is small compared to the load on the one that is fed back. regulation also improves if the load-current range is limited. consult the transformer manufacturer for the proper design for a given application. transformerless inverter for negative ccd bias (aux2, max1567) on the max1567, aux2 is set up to drive an external p- channel mosfet in an inverting configuration. dl2 drives low to turn on the mosfet, and fb2 has inverted polarity and a 0v threshold. this is useful for generating negative ccd bias without a transformer, particularly with high pixel-count cameras that have a greater negative ccd load current. figure 10 shows an example circuit. boost with charge pump for positive and negative outputs another method of producing bipolar output voltages without a transformer is with an aux controller and a charge-pump circuit, as shown in figure 11. when mos- fet q1 turns off, the voltage at its drain rises to supply current to v out+ . at the same time, c1 charges to the voltage v out+ through d1. when the mosfet turns on, c1 discharges through d3, thereby charging c3 to v out - minus the drop across d3 to create roughly the same voltage as v out+ at v out- , but with inverted polarity.
max1566/max1567 six-channel, high-efficiency, digital camera power supplies ______________________________________________________________________________________ 33 if different magnitudes are required for the positive and negative voltages, a linear regulator can be used at one of the outputs to achieve the desired voltages. one such connection is shown in figure 12. this circuit is somewhat unique in that a positive-output linear regu- lator can regulate a negative voltage output. it does this by controlling the charge current flowing to the flying capacitor rather than directly regulating at the output. sepic boost-buck the max1566/max1567s?internal switch step-up, main, and step-down converters can be cascaded to make a high-efficiency boost-buck converter, but it is sometimes desirable to build a second boost-buck converter with an aux_ controller. one type of step-up/step-down converter is the sepic, shown in figure 13. inductors l1 and l2 can be sepa- rate inductors or can be wound on a single core and coupled like a transformer. typically, a coupled inductor improves efficiency since some power is transferred through the coupling so less power passes through the coupling capacitor (c2). likewise, c2 should have low esr to improve efficiency. the ripple-current rating must be greater than the larger of the input and output cur- rents. the mosfet (q1) drain-source voltage rating and the rectifier (d1) reverse-voltage rating must exceed the sum of the input and output voltages. other types of step-up/step-down circuits are a flyback converter and a step-up converter followed by a linear regulator. adding a max1801 slave the max1801 is a 6-pin, sot-slave, dc-to-dc controller that can be connected to generate additional output volt- ages. it does not generate its own reference or oscillator. instead, it uses the reference and oscillator of the max1566/max1567 (figure 14). the max1801 controller operation and design are similar to that of the max1566/max1567 aux controllers. all comments in the aux controller component selection section also apply to add-on max1801 slave controllers. for more details, refer to the max1801 data sheet. applications for status outputs the max1566/max1567 have three status outputs: sdok , aux1ok , and scf. these monitor the output of the step-down channel, the aux1 channel, and the sta- tus of the overload-short-circuit protection. each output is open drain to allow the greatest flexibility. figures 15, 16, and 17 show some possible connections for these outputs. using sdok and aux1ok for power sequencing sdok goes low when the step-down reaches regula- tion. some microcontrollers with low-voltage cores require that the high-voltage (3.3v) i/o rail not be pow- ered up until the core has a valid supply. the circuit in figure 15 accomplishes this by driving the gate of a pfet connected between the 3.3v output and the processor i/o supply. figure 16 shows a similar application where aux1ok gates 5v power to the ccd only after the +15v output is in regulation. alternately, power sequencing can also be implement- ed by connecting rc networks to delay the appropriate converter on_ inputs. using scf for full-load startup the scf output goes low only after the step-up reaches regulation. it can be used to drive a p-channel mosfet switch that turns off the load of a selected supply in the event of an overload. or, it can remove the load until the supply reaches regulation, effectively allowing full- load startup. figure 17 shows such a connection for the step-up output. setting v sd below 1.25v the step-down feedback voltage is 1.25v. with a stan- dard two-resistor feedback network, the output voltage can be set to values between 1.25v and the input volt- age. if a step-down output voltage less than 1.25v is desired, it can be set by adding a third feedback resis- tor from fbsd to a voltage higher than 1.25v. the step- up or main outputs are convenient for this, as shown in figure 18. the equation governing output voltage in figure 18? circuit is as follows: 0 = [(v sd - v fbsd ) / r1] + [(0 - v fbsd ) / r2] + [(v su - v fbsd ) / r3] where v sd is the output voltage, v fbsd is 1.25v, and v su is the step-up output voltage. any available volt- age that is higher than 1.25v can be used as the con- nection point for r3 in figure 18, and for the v sd term in the equation. since there are multiple solutions for r1, r2, and r3, the above equation cannot be written in terms of one resistor. the best method for determin- ing resistor values is to enter the above equation into a spreadsheet and test estimated resistor values. a good starting point is with 100k ? at r2 and r3.
max1566/max1567 six-channel, high-efficiency, digital camera power supplies designing a pc board good pc board layout is important to achieve optimal performance from the max1566/max1567. poor design can cause excessive conducted and/or radiated noise. conductors carrying discontinuous currents and any high-current path should be made as short and wide as possible. a separate low-noise ground plane contain- ing the reference and signal grounds should connect to the power-ground plane at only one point to minimize the effects of power-ground currents. typically, the ground planes are best joined right at the ic. keep the voltage-feedback network very close to the ic, preferably within 0.2in (5mm) of the fb_ pin. nodes with high dv/dt (switching nodes) should be kept as small as possible and should be routed away from high-impedance nodes such as fb_. refer to the max1566/max1567 ev kit data sheet for a full pc board example. chip information transistor count: 9420 process: bicmos 34 ______________________________________________________________________________________
max1566/max1567 six-channel, high-efficiency, digital camera power supplies maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 35 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) qfn thin 6x6x0.8 .eps e e l l a1 a2 a e/2 e d/2 d e2/2 e2 (ne-1) x e (nd-1) x e e d2/2 d2 b k k l c l c l c l c l e 1 2 21-0141 package outline 36, 40, 48l thin qfn, 6x6x0.8mm l1 l e 8. coplanarity applies to the exposed heat sink slug as well as the terminals. 6. nd and ne refer to the number of terminals on each d and e side respectively. 5. dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from terminal tip. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 9. drawing conforms to jedec mo220, except for 0.4mm lead pitch package t4866-1. 7. depopulation is possible in a symmetrical fashion. 3. n is the total number of terminals. 2. all dimensions are in millimeters. angles are in degrees. 1. dimensioning & tolerancing conform to asme y14.5m-1994. notes: 10. warpage shall not exceed 0.10 mm. e 2 2 21-0141 package outline 36, 40, 48l thin qfn, 6x6x0.8mm

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